Call for Papers

MTIC 2027 solicits original, unpublished research papers. Topics of interest include, but are not limited to, the following six areas:

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Track 1 Advanced Memory Devices and Processes

1. Device physics and process technologies for advanced DRAM, SRAM, and flash memory (3D NAND) 2. Device design and optimization of emerging non-volatile memories (PCRAM, RRAM, MRAM, FeRAM) 3. Co-Design of Computational Optics and AI 4. Modeling, characterization, and reliability analysis of memory devices at the nanoscale 5. Advanced channel materials and selective processes for memory arrays 6. Compatible integration of embedded memory devices with logic processes

Track 2 Memory Circuit and Architecture Design

1. High-speed and low-power read and write circuit design for SRAM, DRAM, and flash memory 2. Circuit and interface design for high-density embedded memories (eNVM, eMRAM, etc.) 3. Memory array and peripheral circuit design for 3D integration 4. Circuit and architecture implementation of near-memory computing 5. Error correction coding (ECC), fault tolerance, and reliability enhancement circuits for memories 6. Memory-based physical unclonable function (PUF) and hardware security circuit design

Track 3 3D Integration, Advanced Packaging, and Heterogeneous Integration

1. Monolithic three-dimensional integration technologies for 3D NAND, 3D DRAM, and 3D-SRAM 2. Memory-logic 3D stacking based on through-silicon vias (TSVs) and hybrid bonding 3. Heterogeneous integration of memory and compute chiplets under chiplet architectures 4. 2.5D/3D packaging and interface technologies for high-bandwidth memory (HBM) 5. Signal integrity, power integrity, and thermal management in advanced packaging 6. Three-dimensional integration of heterogeneous materials (e.g., oxide semiconductors, two-dimensional materials) with silicon substrates

Track 4 Design Automation and Testing for Memory and Integrated Circuits

1. Memory compiler design and design-technology co-optimization (DTCO) 2. Architecture exploration and automated design tools for processing-in-memory chips 3. Built-in self-test (BIST) and repair techniques for large-scale memory arrays 4. Test access mechanisms and yield analysis for 3D memory chips 5. Parasitic extraction and layout optimization for memory circuits at advanced process nodes 6. System-level design space exploration for integrated memory and computing

Track 5 Reliability and Hardware Security of Integrated Circuits and Memory Systems

1. Ensuring stable and secure operation of chips across diverse application scenarios. 2. Soft error tolerance and radiation hardening design for memories in advanced process technologies 3. Aging modeling, lifetime prediction, and online health monitoring of memories 4. Hardware Trojan detection and side-channel attack protection for memory arrays 5. Physical unclonable functions (PUFs) and true random number generators based on memory physical characteristics 6. Fault-tolerant memory architectures for automotive electronics and high-reliability scenarios 7. Lightweight hardware security and trusted execution environments for edge AI devices

Track 6 Memory and Integrated Circuit Systems for Emerging Applications

1. Processing-in-memory co-design for edge AI and on-device large model inference 2. High-reliability memory and real-time computing systems for autonomous driving and intelligent cockpits 3. Intelligent memory and signal processing integrated circuit systems for 6G communications 4. Low-power memory and processing chip systems for biomedical electronics and brain-computer interfaces 5. Memory hierarchy optimization and processing-in-memory collaboration in data centers and cloud computing 6. Energy-harvesting intelligent memory and sensing-computing systems for the Internet of Things (IoT)